1. Field of the Invention
The invention relates to semiconductor devices and more particularly to the packaging of two or more such devices within one package.
2. Description of the Prior Art
In high frequency transistor packages the inherent inductance and capacitance caused by bonding wires and metallic pads contribute to the bandwidth, power loss, and ultimate impedance matching capability of the device. In the past, these devices have been constructed by placing the input and output pads in a spaced relationship with a ground plane so that the circuit exhibits a transmission line characteristic with respect to the ground plane.
U.S. Pat. No. 3,713,006, which issued to Litty et al. on Jan. 23, 1973, is an example of a packaging technique for RF and microwave transistors which uses a number of transistors formed on a common die which are wired in parallel to provide a high power device. In order to achieve higher and higher power outputs, the approach has been to wire more and more transistors in parallel. The disadvantage of this is that the parasitic reactances associated with the transistor die and associated packaging leads cause the impedance levels to decrease and thus become an important part of the equivalent input and output circuit.
The bandwidth, internal power loss, input and output impedance levels, and impedance matching characteristics are all related to parasitic reactances created by the lead bonds within the package and the parasitic elements associated with the transistor die.
In U.S. Pat. No. 3,969,752, which issued to Martin et al. on July 13, 1976, a compensating circuit is formed by a shunt reactance which is equal to the shunt parasitic capacitance at the output of the transistor die. The shunt reactance resonates with the parasitic capacitance to thereby cancel out the reactance characteristic in the equivalent circuit. The reactance branch which includes a capacitance in series with an inductance is connected in parallel with the shunt die capacitance. The series capacitance is necessary in order to block the DC currents from the ground plane which otherwise would short out the transistor output through the inductance to ground. The inductance is provided by either a lumped tuning wire or a high impedance transmission line connected from the capacitance to the transistor die of the device. In either case, the prior circuit is necessarily complicated by the fact that bond wires must be used in order to connect the various elements of the circuit together. It is very difficult to always attain the same length of bond wire in a manufacturing process and therefore this circuit tends to be very difficult to reproduce in mass production. Furthermore, the series capacitor introduces further loss characteristics which degrade the efficiency of the transistor circuit. The necessity of having a capacitor introduces one more potential element to fail and thus decreases the overall reliability of the device.